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1 ads7818 ads7818 ads7818 description the ads7818 is a 12-bit sampling analog-to-digital converter (a/d) complete with sample/hold, internal 2.5v reference, and synchronous serial interface. typi- cal power dissipation is 11mw at a 500khz through- put rate. the device can be placed into a power down mode which reduces dissipation to just 2.5mw. the input range is zero to two times the reference voltage, and the internal reference can be overdriven by an external voltage. low power, small size, and high-speed make the ads7818 ideal for battery operated systems such as wireless communication devices, portable multi-chan- nel data loggers, and spectrum analyzers. the serial interface also provides low-cost isolation for remote data acquisition. the ads7818 is available in a plas- tic mini-dip-8 or an msop-8 package and is guaran- teed over the C40 c to +85 c temperature range. 12-bit high speed low power sampling analog-to-digital converter features l 500khz throughput rate l 2.5v internal reference l low power: 11mw l single supply +5v operation l differential input l serial interface l guaranteed no missing codes l mini-dip-8 and msop-8 l unipolar input range international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 applications l battery operated systems l digital signal processing l high speed data acquisition l wireless communication systems ? 1998 burr-brown corporation pds-1408b printed in u.s.a. may, 2000 sar clk serial interface comparator s/h amp data +in ?n cdac internal +2.5v ref buffer v ref conv 10k w ?0% for most current data sheet and other product information, visit www.burr-brown.com sbas078
2 ads7818 specifications at t a = C40 c to +85 c, +v cc = +5v, f sample = 500khz, f clk = 16 ? f sample , internal reference, unless otherwise specified. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any th ird party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. ads7818p, e ads7818pb, eb parameter conditions min typ max min typ max units analog input full-scale input span (1) +in C (Cin) 0 5 [[ v absolute input range +in C0.2 v cc +0.2 [[ v Cin C0.2 +0.2 [[ v capacitance 15 [ pf leakage current 1 [ m a system performance resolution 12 [ bits no missing codes 12 [ bits integral linearity error 1 2 0.5 1 lsb (2) differential linearity error 0.8 0.5 1 lsb offset error 2 5 1 [ lsb gain error (3) 25 c 12 30 7 15 lsb C40 c to +85 c 50 35 lsb common-mode rejection dc, 0.2vp-p 70 [ db 1mhz, 0.2vp-p 50 [ db noise 150 [ m vrms power supply rejection worst case d , +v cc = 5v 5% 1.2 [ lsb sampling dynamics conversion time 1.625 [ m s acquisition time 0.350 [ m s throughput rate 500 [ khz aperture delay 5 [ ns aperture jitter 30 [ ps step response 350 [ ns dynamic characteristics signal-to-noise ratio v in = 5vp-p at 100khz 72 [ db total harmonic distortion (4) v in = 5vp-p at 100khz C78 C72 C82 C75 db signal-to-(noise+distortion) v in = 5vp-p at 100khz 68 70 70 72 db spurious free dynamic range v in = 5vp-p at 100khz 72 78 75 82 db usable bandwidth sinad > 68db 350 [ khz reference output voltage i out = 0 2.475 2.50 2.525 2.48 [ 2.52 v source current (5) static load 50 [ m a drift i out = 0 20 [ ppm / c line regulation 4.75v v cc 5.25v 0.6 [ mv reference input range 2.0 2.55 [[ v resistance (6) to internal reference voltage 10 [[[ k w digital input/output logic family cmos [ logic levels: v ih |i ih | +5 m a 3.0 v cc +0.3 [[ v v il |i il | +5 m a C0.3 0.8 [[ v v oh i oh = C500 m a 3.5 [[ v v ol i ol = 500 m a 0.4 [[ v data format straight binary [ power supply requirement +v cc specified performance 4.75 5.25 [[ v quiescent current f sample = 500khz 2.2 [ ma power down 0.5 [ ma power dissipation f sample = 500khz 11 20 [[ mw power down 2.5 [ mw temperature range specified performance C40 +85 [[ c [ specifications same as ads7818p,e. notes: (1) ideal input span, does not include gain or offset error. (2) lsb means least significant bit, with v ref equal to +2.5v, one lsb is 1.22mv. (3) measured relative to an ideal, full-scale input (+in C (Cin)) of 4.999v. thus, gain error includes the error of the internal voltage ref erence. (4) calculated on the first nine harmonics of the input frequency. (5) if the internal reference is required to source current to an external load, the referenc e voltage will change due to the internal 10k w resistor. (6) can vary 30%.
3 ads7818 +v cc to gnd ............................................................................ C0.3v to 6v analog inputs to gnd .............................................. C0.3v to (v cc + 0.3v) digital inputs to gnd ............................................... C0.3v to (v cc + 0.3v) power dissipation .......................................................................... 325mw maximum junction temperature ................................................... +150 c operating temperature range ......................................... C40 c to +85 c storage temperature range .......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum condi- tions for extended periods may affect device reliability. electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. burr- brown corporation recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. absolute maximum ratings (1) pin configuration top view 1 2 3 4 8 7 6 5 +v cc clk data conv v ref +in ?n gnd ads7818 plastic mini-dip-8 pin name description 1v ref reference output. decouple to ground with a 0.1 m f ceramic capacitor and a 2.2 m f tantalum capacitor. 2 +in non-inverting input. 3 Cin inverting input. connect to ground or to remote ground sense point. 4 gnd ground. 5 conv convert input. controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and power down mode. see the digital interface section for more information. 6 data serial data output. the 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge of clk. by properly controlling the conv input, it is possibly to have the data transmitted least significant bit first. see th e digital interface section for more information. 7 clk clock input. synchronizes the serial data transfer and determines conversion speed. 8+v cc power supply. decouple to ground with a 0.1 m f ceramic capacitor and a 10 m f tantalum capacitor. pin assignments 1 2 3 4 8 7 6 5 +v cc clk data conv v ref +in ?n gnd ads7818 msop-8 package/ordering information maximum maximum integral differential linearity linearity package specification error error drawing temperature package ordering transport product (lsb) (lsb) package number (1) range marking (2) number (3) media ads7818e 2 n/s (4) msop-8 337 C40 c to +85 c a18 ads7818e/250 tape and reel "" " " " " " ads7818e/2k5 tape and reel ads7818eb 1 1 msop-8 337 C40 c to +85 c a18 ads7818eb/250 tape and reel "" " " " " " ads7818eb/2k5 tape and reel ads7818p 2 n/s (4) plastic dip-8 006 C40 c to +85 c ads7818p ads7818p rails ads7818pb 1 1 "" " ads7818pb ads7818pb rails note: (1) for detail drawing and dimension table, please see end of data sheet or package drawing file on web. (2) performance grade information is marked on the reel. (3) models with a slash(/) are available only in tape and reel in quantities indicated (e.g. /250 indicates 250 un its per reel, /2k5 indicates 2500 devices per reel). ordering 2500 pieces of ads7818e/2k5 will get a single 2500-piece tape and reel. for detailed tape and reel mechan ical information, refer to the www.burr-brown.com web site under applications and tape and reel orientation and dimensions. (4) n/s = not specified, typical o nly. however, 12-bits no missing codes is guaranteed over temperature.
4 ads7818 typical performance curves at t a = +25 c, v cc = +5v, f sample = 500khz, f clk = 16 ? f sample , and internal +2.5v reference, unless otherwise specified. change in integral linearity and differential linearity vs sample rate 400 100 600 200 300 500 sample rate (khz) delta from f sample = 500khz (lsb) ?.3 0.4 0.3 0.2 0.1 0.0 ?.1 ?.2 change in differential linearity (lsb) change in integral linearity (lsb) change in offset vs temperature 20 ?0 100 ?0 0 40 temperature ( c) delta from 25 c (lsb) ?.4 2.0 1.6 1.2 0.8 0.4 0.0 60 80 power-down supply current vs temperature 20 ?0 100 ?0 0 40 temperature (?) power-down supply current (?) 390 470 440 430 420 410 400 450 460 60 80 supply current vs temperature 20 ?0 100 ?0 0 40 temperature (?) supply current (ma) 1.6 2.3 2.1 2.0 1.9 1.8 1.7 2.2 60 80 f sample = 500khz f sample = 125khz supply current vs sample rate 400 100 600 200 300 500 sample rate (khz) supply current (ma) 1.7 2.4 2.3 2.2 2.1 2.0 1.9 1.8 change in full-scale error vs temperature 20 ?0 100 ?0 0 40 temperature ( c) delta from 25 c (lsb) ?0 2 0 ? ? ? ? 60 80
5 ads7818 typical performance curves (cont.) at t a = +25 c, v cc = +5v, f sample = 500khz, f clk = 16 ? f sample , and internal +2.5v reference, unless otherwise specified. power supply rejection vs power supply ripple frequency 1 10 100 1k 10k 100k 1m power supply ripple frequency (hz) power supply rejection (mv/v) 30 25 20 15 10 5 0 0 frequency spectrum (4096 point fft; f in = 10.9khz, ?.2db) 0 250 62.5 187.5 125 frequency (khz) amplitude (db) ?20 ?00 ?0 ?0 ?0 ?0 0 frequency spectrum (4096 point fft; f in = 102khz, ?.2db) amplitude (db) ?00 ?0 ?0 ?0 ?0 0 250 62.5 187.5 125 frequency (khz) ?20 change in full-scale error vs external reference voltage 2.3 2.0 2.5 2.1 2.2 2.4 external reference voltage (v) delta from v ref = 2.5v (mv) ?.2 0.2 ?.4 ?.6 ?.8 ?.0 ?.2 0.0 change in offset vs external reference voltage 2.5 1.9 3.1 2.1 2.3 2.7 2.9 external reference voltage (v) delta from v ref = 2.5v (mv) ?.4 0.5 0.0 ?.1 ?.2 ?.3 0.1 0.2 0.3 0.4 peak-to-peak noise vs external reference voltage 2.3 2.0 2.5 2.1 2.2 2.4 external reference voltage (lsb) peak-to-peak noise (lsb) 0.40 0.70 0.65 0.60 0.55 0.50 0.45
6 ads7818 typical performance curves (cont.) at t a = +25 c, v cc = +5v, f sample = 500khz, f clk = 16 ? f sample , and internal +2.5v reference, unless otherwise specified. change in signal-to-noise ratio and signal-to-(noise+distortion) vs temperature ?0 ?0 100 temperature ( c) delta from +25 c (db) 0.2 0.1 0.0 ?.1 ?.2 ?.3 0.3 0 20 40 60 80 sinad snr f in = 100khz, ?.2db change in spurious free dynamic range and total harmonic distortion vs temperature ?0 ?0 100 temperature ( c) sfdr delta from +25 c (db) thd delta from +25 c (db) 0.5 0.0 ?.5 ?.0 ?.5 ?.0 1.0 ?.5 0.0 0.5 1.0 1.5 2.0 ?.0 0 20 40 60 80 thd i sfdr i first nine harmonics f in = 100khz, ?.2db of the input frequency 0 frequency spectrum (4096 point fft; f in = 247khz, ?.2db) amplitude (db) ?00 ?0 ?0 ?0 ?0 0 250 62.5 187.5 125 frequency (khz) ?20 spurious free dynamic range and total harmonic distortion vs input frequency 10k 100k 1k 1m input frequency (hz) sfdr (db) thd (db) 85 80 75 70 65 90 85 80 75 70 65 90 thd i i first nine harmonics of the input frequency sfdr signal-to-noise ratio and signal-to-(noise+distortion) vs input frequency 10k 100k 1k 1m input frequency (hz) snr and sinad (db) 74 72 70 68 66 64 76 sinad snr
7 ads7818 figure 1. basic operation of the ads7818. theory of operation the ads7818 is a high speed successive approximation register (sar) analog-to-digital converter (a/d) with an internal 2.5v bandgap reference. the architecture is based on capacitive redistribution which inherently includes a sample/hold function. the converter is fabricated on a 0.6 m cmos process. see figure 1 for the basic operating circuit for the ads7818. the ads7818 requires an external clock to run the conver- sion process. this clock can vary between 200khz (12.5hz throughput) and 8mhz (500khz throughput). the duty cycle of the clock is unimportant as long as the minimum high and low times are at least 50ns and the clock period is at least 125ns. the minimum clock frequency is set by the leakage on the capacitors internal to the ads7818. the analog input is provided to two input pins: +in and Cin. when a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. while a conversion is in progress, both inputs are disconnected from any internal function. the range of the analog input is set by the voltage on the v ref pin. with the internal 2.5v reference, the input range is 0 to 5v. an external reference voltage can be placed on v ref , overdriving the internal voltage. the range for the external voltage is 2.0v to 2.55v, giving an input voltage range of 4.0v to 5.1v. the digital result of the conversion is provided in a serial manner, synchronous to the clk input. the result is pro- vided most significant bit first and represents the result of the conversion currently in progressthere is no pipeline delay. by properly controlling the conv and clk inputs, it is possible to obtain the digital result least significant bit first. analog input the +in and Cin input pins allow for a differential input signal to be captured on the internal hold capacitor when the converter enters the hold mode. the voltage range on the Cin input is limited to C0.2v to 0.2v. because of this, the differential input can be used to reject only small signals that are common to both inputs. thus, the Cin input is best used to sense a remote ground point near the source of the +in signal. if the source driving the +in signal is nearby, the Cin should be connected directly to ground. the input current into the analog input depends on input voltage and sample rate. essentially, the current into the device must charge the internal hold capacitor during the sample period. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance to a 12-bit settling level within the sample periodwhich can be as little as 350ns in some operating modes. while the converter is in the hold mode or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1g w . care must be taken regarding the input voltage on the +in and Cin pins. to maintain the linearity of the converter, the +in input should remain within the range of gnd C 200mv to +v cc + 200mv. the Cin input should not drop below gnd C 200mv or exceed gnd + 200mv. outside of these ranges, the converters linearity may not meet specifications. reference the reference voltage on the v ref pin directly sets the full- scale range of the analog input. the ads7818 can operate with a reference in the range of 2.0v to 2.55v, for a full- scale range of 4.0v to 5.1v. the voltage at the v ref pin is internally buffered and this buffer drives the capacitor dac portion of the converter. this is important because the buffer greatly reduces the dynamic load placed on the reference source. however, the voltage at v ref will still contain some noise and glitches from the sar conversion process. these can be reduced by carefully bypassing the v ref pin to ground as outlined in the sections that follow. internal reference the ads7818 contains an on-board 2.5v reference, result- ing in a 0v to 5v input range on the analog input. the specification table gives the various specifications for the 1 2 3 4 8 7 6 5 +v cc clk data conv v ref +in ?n gnd ads7818 0.1? +5v 0.1? 10? serial clock from microcontroller or dsp serial data convert start + 2.2? + 0 to 5v analog input
8 ads7818 internal reference. this reference can be used to supply a small amount of source current to an external load, but the load should be static. due to the internal 10k w resistor, a dynamic load will cause variations in the reference voltage, and will dramatically affect the conversion result. note that even a static load will reduce the internal reference voltage seen at the buffer input. the amount of reduction depends on the load and the actual value of the internal 10k w resistor. the value of this resistor can vary by 30%. the v ref pin should be bypassed with a 0.1 m f capacitor placed as close as possible to the ads7818 package. in addition, a 2.2 m f tantalum capacitor should be used in parallel with the ceramic capacitor. placement of this ca- pacitor is not as critical. external reference the internal reference is connected to the v ref pin and to the internal buffer via a 10k w series resistor. thus, the reference voltage can easily be overdriven by an external reference voltage. the voltage range for the external voltage is 2.0v to 2.55v, corresponding to an analog input range of 4.0v to 5.1v. while the external reference will not source significant current into the v ref pin, it does have to drive the series 10k w resistor that is terminated into the 2.5v internal reference (the exact value of the resistor will vary up to 30% from part to part). in addition, the v ref pin should still be bypassed to ground with at least a 0.1 m f ceramic capacitor (placed as close to the ads7818 as possible). the reference will have to be stable with this capacitive load. depending on the particular reference and a/d conversion speed, additional bypass capacitance may be required, such as the 2.2 m f tantalum capacitor shown in figure 1. reasons for choosing an external reference over the internal reference vary, but there are two main reasons. one is to achieve a given input range. for example, a 2.048v refer- ence provides for a 0v to 4.095v input rangeor 1mv per lsb. the other is to provide greater stability over tempera- ture. the internal reference is typically 20ppm/ c which translates into a full-scale drift of roughly 1 output code for every 12 c (this does not take into account other sources of full-scale drift). if greater stability over temperature is needed, then an external reference with lower temperature drift will be required. digital interface figure 2 shows the serial data timing and figure 3 shows the basic conversion timing for the ads7818. the specific timing numbers are listed in table i. there are several important items in figure 3 which give the converter addi- tional capabilities over typical 8-pin converters. first, the transition from sample mode to hold mode is synchronous to the falling edge of conv and is not dependent on clk. second, the clk input is not required to be continuous during the sample mode. after the conversion is complete, the clk may be kept low or high. figure 2. serial data and clock timing. symbol description min typ max units t acq acquisition time 350 ns t conv conversion time 1.5 m s t ckp clock period 125 5000 ns t ckl clock low 50 ns t ckh clock high 50 ns t ckdh clock falling to current data 5 15 ns bit no longer valid t ckds clock falling to next data valid 30 50 ns t cvl conv low 40 ns t cvh conv high 40 ns t ckch conv hold after clock falls (1) 10 ns t ckcs conv setup to clock falling (1) 10 ns t ckde clock falling to data enabled 20 50 ns t ckdd clock falling to data 70 100 ns high impedance t cksp clock falling to sample mode 5 ns t ckpd clock falling to power-down mode 50 ns t cvhd conv falling to hold mode 5 ns (aperture delay) t cvsp conv rising to sample mode 5 ns t cvpu conv rising to full power-up 50 ns t cvdd conv changing state to data 70 100 ns high impedance t cvpd conv changing state to 50 ns power-down mode t drp conv falling to start of clk 5 m s (for hold droop < 0.1 lsb) note: (1) this timing is not required under some situations. see text for more information. table i. timing specifications (t a = C40 c to +85 c, c load = 30pf). the asynchronous nature of conv to clk raises some interesting possibilities, but also some design consider- ations. figure 3 shows that conv has timing restraints in relation to clk (t ckch and t ckcs ). however, if these times are violated (which could happen if conv is completely asynchronous to clk), the converter will perform a conver- sion correctly, but the exact timing of the conversion is indeterminate. since the setup and hold time between conv and clk has been violated in this example, the start of conversion could vary by one clock cycle. (note that the start of conversion can be detected by using a pull-up resistor on data. when data drops out of high-imped- ance and goes low, the conversion has started and that clock cycle is this first of the conversion.) in addition if conv is completely asynchronous to clk and clk is continuous, then there is possibility that clk will transition just prior to conv going low. if this occurs data clk t ckh t ckp t ckdh t ckds t ckl
9 ads7818 d11 (msb) data notes: (1) clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ads7818, provided th at the minimum t acq time is met. the clk input may remain high or low during this period. (2) the transition from sample mode to hold mode occurs on the falling edge of conv. this transition is not dependent on clk. (3) the device remains fully powered when operated as shown. if the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device t o enter a power down mode. see the power down timing for more information. hold conversion in progress idle idle ( 3) sample sample (2) (1) hold clk 1 2 3 4 11 12 13 14 15 14 15 16 16 1 conv sample/hold mode internal conversion state d10 d9 d2 d1 d0 (lsb) t ckde t cvhd t conv t acq t ckcs t ckch t cksp t cvl t ckdd t cvck faster than the 10ns indicated by t ckch , then there is a chance that some digital feedthrough may be coupled onto the hold capacitor. this could cause a small offset error for that particular conversion. thus, there are two basic ways to operate the ads7818. conv can be synchronous to clk and clk can be con- tinuous. this would be the typical situation when interfacing the converter to a digital signal processor. the second method involves having conv asynchronous to clk and gating the operation of clk (a non-continuous clock). this method would be more typical of an spi-like interface on a microcontroller. this method would also allow conv to be generated by a trigger circuit and to initiate (after some delay) the start of clk. these two methods are covered under dsp interfacing and spi interfacing. power-down timing the conversion timing shown in figure 3 does not result in the ads7818 going into the power-down mode. if the conversion rate of the device is high (approaching 500khz), then there is very little power that can be saved by using the power-down mode. however, since the power-down mode incurs no conversion penalty (the very first conversion is valid), at lower sample rates, significant power can be saved by allowing the device to go into power-down mode be- tween conversions. figure 4 shows the typical method for placing the a/d into the power-down mode. if conv is kept low during the conversion and is low at the start of the 13 clock cycle, then the device enters the power-down mode. it remains in this mode until the rising edge of conv. note that conv must be high for at least t acq in order to sample the signal properly as well as to power-up the internal nodes. there are two different methods for clocking the ads7818. the first involves scaling the clk input in relation to the conversion rate. for example, an 8mhz input clock and the timing shown in figure 3 results in a 500khz conversion rate. likewise, a 1.6mhz clock would result in a 100khz conversion rate. the second method involves keeping the clock input as close to the maximum clock rate as possible and starting conversions as needed. this timing is similar to that shown in figure 4. as an example, a 50khz conversion rate would require 160 clock periods per conversion instead of the 16 clock periods used at 500khz. the main distinction between the two is the amount of time that the ads7818 remains in power down. in the first mode, the converter only remains in power down for a small number of clock periods (depending on how many clock periods there are per each conversion). as the conversion rate scales, the converter always spends the same percentage of time in power down. since less power is drawn by the digital logic, there is a small decrease in power consump- tion, but it is very slight. this effect can be seen in the typical performance curve supply current vs sample rate. figure 3. basic conversion timing.
10 ads7818 d11 (msb) data hold sample sample hold clk conv sample/hold mode power mode full power full power low power d10 d1 d0 (lsb) t ckpd t cvpu t cvsp 123 1213 t acq conversion in progress idle idle internal conversion state notes: (1) the low power mode (?ower-down? is entered when conv remains low during the conversion and is still low at the start of the 13th clock cycle. (2) the low power mode is exited when conv goes high. (3) when in power-down, the transition fro m hold mode to sample mode is initiated by conv going high. (1) (2) (3) figure 4. power-down timing. d11 (msb) data conversion in progress idle low... idle clk conv power mode full power low power d10 d1 d0 (lsb) 1 2 3 121314 2324 d1 d10 d11 (msb) internal conversion state t cvdd t ckcs t ckch t cvpd t cvh hold sample sample/hold mode notes: (1) the serial data can be transmitted lsb first by pulling conv low during the 13th clock cycle. (2) after the msb has been transmitted, the data output pin will remain low until conv goes high. (3) when conv is taken low to initiate the lsb first tra nsfer, the converter enters the power-down mode. (1) (2) (3) figure 5. serial data lsb-first timing. in contrast, the second method (clocking at a fixed rate) means that each conversion takes x clock cycles. as the time between conversions get longer, the converter remains in power-down an increasing percentage of time. this re- duces total power consumption by a considerable amount. for example, a 50khz conversion rate results in roughly 1/10 of the power (minus the reference) that is used at a 500khz conversion rate.
11 ads7818 table ii offers a look at the two different modes of operation and the difference in power consumption. the conversion will terminate immediately, before all 12-bits have been decided. this can be a very useful feature when a resolution of 12-bits is not needed. an example would be when the converter is being used to monitor an input voltage until some condition is met. at that time, the full resolution of the converter would then be used. short-cycling the conversion can result in a faster conversion rate or lower power dissipation. there are several very important items shown in figure 6. the conversion currently in progress is terminated when conv is taken high during the conversion and then taken low prior to t ckch before the start of the 13th clock cycle. note that if conv goes low during the 13th clock cycle, then the lsb first mode will be entered (figure 5). also, when conv goes low, the data output immediately transitions to high impedance. if the output bit that is present during that clock period is needed, conv must not go low until the bit has been properly latched into the receiving logic. data format the ads7818 output data is in straight binary format as shown in figure 7. this figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. power with power with f sample clk = 16 ? f sample clk = 8mhz 500khz 11mw 11mw 250khz 10mw 7mw 100khz 9mw 4mw table ii. power consumption versus clk input. lsb first data timing figure 5 shows a method to transmit the digital result in a least-significant bit (lsb) format. this mode is entered when conv is pulled high during the conversion (before the end of the 12th clock) and then pulled low during the 13th clock (when d0, the lsb, is being transmitted). the next 11 clocks then repeat the serial data, but in an lsb first format. the converter enters the power-down mode during the 13th clock and resumes normal operation when conv goes high. short-cycle timing the conversion currently in progress can be short-cycled with the technique shown in figure 6. this term means that figure 6. short-cycle timing. d11 (msb) data conversion in progress idle idle clk conv power mode full power low power d10 d8 d9 d7 123 5 467 d6 internal conversion state t cvdd t cvl t cvh hold sample sample/hold mode note: (1) the conversion currently in progress can be stopped by pulling conv low during the conversion. this must occur at least t ckcs prior to the start of the 13th clock cycle. the data output pin will tri-state and the device will enter the power-down mode when conv is pulled low. (1) t cvpd
12 ads7818 d11 (msb) data clk conv d10 d1 d0 (lsb) 23 1 4 13 14 15 16 1 2 3 d11 (msb) t acq t drp input voltage (2) (v) output code 0v fs = full-scale voltage = 2 ?v ref 1 lsb = fs/4096 4.999v (1) 00...010 00...001 00...000 11...101 11...110 11...111 1 lsb notes: (1) for external reference, value is 2 v ref ?1 lsb. (2) voltage at converter input: +in ( in). figure 7. ideal input voltages and output codes. dsp interfacing figure 8 shows a timing diagram that might be used with a typical digital signal processor such as a ti dsp. for the buffered serial port (bsp) on the tms320c54x family, conv would tied to bfsx, clk would be tied to bclkx, and data would be tied to bdr. spi/qspi interfacing figure 9 shows the timing diagram for a typical serial peripheral interface (spi) or queued serial peripheral inter- face (qspi). such interfaces are found on a number of microcontrollers form various manufacturers. conv would be tied to a general purpose i/o pin (spi) or to a pcx pin (qspi), clk would be tied to the serial clock, and data would be tied to the serial input data pin such as miso (master in slave out). note the time t drp shown in figure 9. this represents the maximum amount of time between conv going low and the start of the conversion clock. since conv going low places the sample and hold in the hold mode and because the hold capacitor looses charge over time, there is a require- ment that time t drp be met as well as the maximum clock period (t ckp ). layout for optimum performance, care should be taken with the physical layout of the ads7818 circuitry. this is particu- larly true if the clk input is approaching the maximum input rate. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connec- tions, and digital inputs that occur just prior to latching the output of the analog comparator. thus, during any single conversion for an n-bit sar converter, there are n win- dows in which large external transient voltages can easily affect the conversion result. such glitches might originate from switching power supplies, nearby digital logic, and high power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. the error can change if the external event changes in time with respect to the clk input. figure 8. typical dsp interface timing. d11 (msb) data clk conv d10 d1 d0 (lsb) 12 15 16 3 12 13 14 15 16 1 2 3 4 d11 (msb) d10 d9 figure 9. typical spi/qspi interface timing.
13 ads7818 with this in mind, power to the ads7818 should be clean and well bypassed. a 0.1 m f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 m f to 10 m f capacitor is recommended. if needed, an even larger capacitor and a 5 w or 10 w series resistor my be used to lowpass filter a noisy supply. the ads7818 draws very little current from an external reference on average as the reference voltage is internally buffered. however, glitches from the conversion process appear at the v ref input and the reference source must be able to handle this. whether the reference is internal or external, the v ref pin should be bypassed with a 0.1 m f capacitor. an additional larger capacitor may also be used, if desired. if the reference voltage is external and originates from an op-amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. the gnd pin should be connected to a clean ground point. in many cases, this will be the analog ground. avoid connections which are too near the grounding point of a microcontroller or digital signal processor. if needed, run a ground trace directly from the converter to the power supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples ads7818e/250 active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818e/250g4 active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818e/2k5 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818e/2k5g4 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818eb/250 active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818eb/250g4 active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818eb/2k5 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818eb/2k5g4 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 85 a18 ads7818p active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type -40 to 85 ads7818p ads7818pb active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type -40 to 85 ads7818p b ADS7818PBG4 active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type -40 to 85 ads7818p b ads7818pg4 active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type -40 to 85 ads7818p (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 11-apr-2013 addendum-page 2 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads7818e/250 vssop dgk 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 ads7818e/2k5 vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 ads7818eb/250 vssop dgk 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 ads7818eb/2k5 vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 package materials information www.ti.com 16-aug-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads7818e/250 vssop dgk 8 250 210.0 185.0 35.0 ads7818e/2k5 vssop dgk 8 2500 367.0 367.0 35.0 ads7818eb/250 vssop dgk 8 250 210.0 185.0 35.0 ads7818eb/2k5 vssop dgk 8 2500 367.0 367.0 35.0 package materials information www.ti.com 16-aug-2012 pack materials-page 2

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